Manufacturing method of semiconductor device with filling insulating film into trench

ABSTRACT

Forming of a first silicon oxide film is started on an internal surface of a trench formed on a surface or upwardly of a semiconductor substrate according to an HDP technique. Then, deposition of the first silicon oxide film stops before an opening of the trench closes. Further, the first silicon oxide film deposited in the vicinity of an opening is etched, and a second silicon oxide film is formed on the first silicon oxide film deposited on the bottom of the trench according to the HDP technique. In this manner, the first and second silicon oxide films can be laminated on the bottom of the trench.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims the benefit of priorityfrom prior Japanese Patent Application P2001-286754 filed on Sep. 20,2001; the entire contents of which are incorporated by reference herein.

BACKGROUND OF THE INVENTION

[0002] The present invention relates to a method for filling a trenchthat is formed in a production process of a semiconductor device.Particularly, the present invention relates to a method for filling thetrench with a high aspect ratio by using a high density plasma (HDP)technique. Further, the present invention relates to the Shallow TrenchIsolation (STI) technique with a high isolation resistance.

[0003] The minute isolation is required in the manufacturing ofsemiconductor devices, along with the shrink of the semiconductor devicein recent years. STI has been used. And, the shrink of STI area is alsobeing carried out for the same purpose. The width of the opening of theSTI trench becomes narrow and the depth of it becomes deep. That is, theaspect ratio that is the ratio of the depth to the width of the openingincreases. Thus, the process filling an insulator into the trench withhigh aspect ratio is needed in forming the STI area.

[0004] The silicon oxide (SiO₂) film by HDP chemical vapor deposition (CV D) (hereinafter, this silicon oxide film is called an HDP film) isfilled into the high aspect trench. However, the aspect ratio of thetrench of STI area increases with the further shrink of thesemiconductor device in recent years. A trench exceeding a high aspectratio of 3 is not able to fill even by the HDP film. When the HDP filmis filled into the trench on a silicon substrate, the upper part of thetrench is closed with the HDP film. A void results within a trench. Thetrench cannot completely fill.

[0005] Also, the STI area, whose width is narrow and isolationperformance is high, is required in the device that uses the highvoltage such as EEPROM (electrically erasable programmable read onlymemory). The STI area, whose width is narrow and isolation performanceis high, has a deep trench. The aspect ratio of the trench becomes veryhigh in the STI area of the cell array of the EEPROM. The filling of theHDP film into the deep trench was difficult.

SUMMARY OF THE INVENTION

[0006] A manufacturing method of a semiconductor device according toembodiments of the present invention includes forming a trench on asurface of a semiconductor substrate, oxidizing thermally a side faceand a bottom face what is called internal surface of the trench, forminga first silicon oxide film into the trench with an HDP, removing thefirst silicon oxide film formed on the side face until a part of theside face is exposed, oxidizing thermally the part of the side faceexposed, and forming a second silicon oxide film on the first siliconoxide film and on the side face with an HDP.

[0007] A manufacturing method of a semiconductor device according toembodiments of the present invention includes forming a trench on asurface of a semiconductor substrate, forming a first silicon oxide filminto the trench with an HDP, removing the first silicon oxide filmformed on the surface until the surface is exposed, and forming a secondsilicon oxide film on the first silicon oxide film and on the exposedsurface with an HDP.

[0008] A manufacturing method of a semiconductor device according toembodiments of the present invention includes forming an insulating filmon a semiconductor substrate, forming a polysilicon film on theinsulating film, forming a trench penetrating the insulating film andthe polysilicon film and dug in the semiconductor substrate, forming athermal oxide film on an internal surface of the trench by a oxidationof an oxygen radical, and filling a first silicon oxide film into thetrench with an HDP.

[0009] A manufacturing method of a semiconductor device according toembodiments of the present invention includes forming an insulating filmon a semiconductor substrate, forming a polysilicon film on theinsulating film, forming a trench penetrating the insulating film andthe polysilicon film and dug in the semiconductor substrate, forming afirst thermal oxide film and a second thermal oxide film by a thermaloxidation of the semiconductor substrate and the polysilicon film on aninternal surface of the trench, forming a first silicon oxide film onthe first thermal oxide film and the second thermal oxide film with anHDP, removing the first silicon oxide film formed on an upper part ofthe second thermal oxide film, and forming a second silicon oxide filmon the first silicon oxide film with an HDP.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010]FIG. 1A and FIG. 1B are sectional views each showing anintermediate stage of manufacturing an earlier semiconductor device;

[0011]FIG. 2A to FIG. 2K are sectional views showing each stage of amethod for manufacturing a semiconductor device of a first embodiment;

[0012]FIG. 3A to FIG. 3E are sectional views showing each stage of amethod for manufacturing a semiconductor device of a second embodiment;

[0013]FIG. 4A to FIG. 4H are sectional views showing each stage of amethod for manufacturing a semiconductor device of a third embodiment;

[0014]FIG. 5A to FIG. 5K are sectional views showing each stage of amethod for manufacturing a semiconductor device of a fourth embodiment;

[0015]FIG. 6A to FIG. 6F are sectional views showing each stage of amethod for manufacturing a semiconductor device of a fifth embodiment;

[0016]FIG. 7A to FIG. 7F are sectional views showing each stage of amethod for manufacturing a semiconductor device of a sixth embodiment;

[0017]FIG. 8A to FIG. 8F are sectional views showing each stage of amethod for manufacturing a semiconductor device of a seventh embodiment;

[0018]FIG. 9A to FIG. 9P are sectional views showing each stage of amethod for manufacturing a semiconductor device of an eighth embodimentfor filling between gate electrodes;

[0019]FIG. 10A to FIG. 10I are sectional views showing each stage of amethod for manufacturing a semiconductor device of a ninth embodimentfor filling between interconections;

[0020]FIG. 11A to FIG. 11M are sectional views showing each stage of amethod for manufacturing a semiconductor device of a tenth embodimentfor an isolation between an internal low voltage resistant circuit and ahigh voltage resistant circuit at a peripheral section, where the leftside of each of these figures is a sectional view showing an internalcircuit area of the semiconductor device for each manufacturing stage;the center of each of these figures is a sectional view similarlyshowing a peripheral circuit area, and the right side of each of thesefigures is a sectional view showing a mask alignment mark area; and

[0021]FIG. 12A to FIG. 12H are sectional views showing each stage of amethod for manufacturing a semiconductor device of an eleventhembodiment.

DETAILED DESCRIPTION OF EMBODIMENTS

[0022] Various embodiments of the present invention will be describedwith reference to the accompanying drawings. It is to be noted that thesame or similar reference numerals are applied to the same or similarparts and elements throughout the drawings, and the description of thesame or similar parts and elements will be omitted or simplified.

[0023] (Reason Why HDP Film Cannot be Filled in)

[0024] A trench exceeding the high aspect rate of 3 cannot be filled ineven with an HDP film 36. As shown in FIG. 1A, the HDP film 36 is filledin a trench provided on a silicon substrate 1. An HDP film 37 closes theupper part of the trench. A void 32 is formed on the HDP film 36. Thetrench cannot be completely filled.

[0025] The Inventor studied in earnest the reasons for the HDP filmbeing unable to fill in a trench exceeding an aspect ratio of 3. As aresult, two reasons came to light.

[0026] The first reason is that, when a trench is filled in with the HDPfilm, the HDP film 37 deposited onto the mask 3 is deposited at the endof the top face of the mask 3. The HDP film 7 on the end of the top faceof the mask 3 is easily sputtered. The corners of the HDP film 37 becomerounded. This rounded portion reflects ions flying upward, and theflying direction is changed to a diagonal direction without the ionsbeing deposited. There is a side face of the trench, particularly a sideface of the mask 3 over the trench in the changed flying direction. Asshown in FIG. 1A, the HDP film 37 is deposited on an upper part of theside face. Before the HDP film 36 filled from the bottom part of thetrench reaches at the upper part of the trench, the HDP film 37 on theside face grows, the trench is completely closed. A large void 32 isproduced. Therefore, in forming an earlier STI area by the HDP film, theaspect ratio exceeds three. The trench is deepened and it takes longertime to fill the HDP film into the trench. The width of the opening ofthe trench is shortened and it takes shorter time to close the opening.And the void 32 has resulted.

[0027] The second reason is the reason why an STI trench with astructure for forming a gate electrode 15 and the STI area 36 in a selfalignment manner cannot be filled. In order to prevent damage to thesilicon (Si) substrate 1 when the HDP film 36 is deposited, beforefilling the HDP film, the internal surface of the trench is oxidized.The thickness of the silicon oxide film is about 10 nm. In this case, inan earlier oxidation method, an oxidation rate strongly depends on thecrystal plane of silicon crystal. Thus, in general a polysilicon (Si)film 15 of which a variety of crystal planes are produced on a surfaceto be oxidized is higher than the silicon substrate in the oxidationrate. The polysilicon film 15 is greatly oxidized. Thus, an oxide filmoxidized of the polysilicon film 15 extends to the center of the trenchfrom the side face of the trench. The opening of the trench is narrowed,and it is difficult to fill the HDP film into the trench.

[0028] (First Embodiment)

[0029] In the first to seventh embodiments, the present invention wasapplied to filling of a trench of an STI area of a semiconductor device.

[0030] A method for manufacturing a semiconductor device of the firstembodiment will be described by referring to FIG. 2A to FIG. 2K. Thesemiconductor device manufacturing method of the first embodiment isdirected to a method for filling in with a HDP film a trench with a highaspect ratio. First, the trench with the high aspect ratio is filledfrom the start to the partway with a HDP film. Next, HDP film depositedon the side face by reflection is removed once. Once again, the HDP filmis deposited. A trench with a high aspect ratio can be filled in the HDPfilm.

[0031] (1) First, as shown in FIG. 2A, a buffer oxide film 2 is formedon a semiconductor substrate 1 according to a thermal oxidation method.Next, as a mask 3, for example, a silicon nitride (Si₃N₄) film is formedaccording to a low pressure (LP) CVD technique.

[0032] (2) As shown in FIG. 2B, a photo resist pattern 4 is formed on aportion serving as an element area according to a photo lithographytechnique.

[0033] (3) Next, as shown in FIG. 2C, the mask 3 is etched using thephoto resist 4 as a mask, and then, a buffer insulating film 2 isetched.

[0034] (4) Further, as shown in FIG. 2D, the semiconductor substrate 1is etched using the mask 3 as a mask, thereby forming a trench 5 withthe high aspect ratio of 5 or more which serves as an isolation area.The opening width of the trench is about 100 nm, for example.

[0035] (5) Then, as shown in FIG. 2E, an HDP film 6 is filled in thetrench 5. When the temperature of substrate 1 is increased toapproximately 650° C., filling characteristics can be optimized. First,the HDP films 6 and 7 are deposited immediately before the HDP film 7deposited at the upper part of the side face of the trench 5 closes theopening to the trench 5. For example, if the HDP film 6 and 7 of thethickness about 300 nm is deposited, the depth filled in with the HDPfilm 6 is also about 300 nm, the film thickness of the HDP film 7 on theside face is about 30 nm, which is about {fraction (1/10)} thereof. Ifthe film 7 of 30 nm is deposited on the side faces at both sides of thetrench 5 of 100 nm in opening width, the remaining opening is 40 nm. Inorder to prevent damage to the silicon substrate 1 when the HDP film 6is deposited, before filling in with the HDP film 6, the inside of thistrench 5 may be oxidized to an oxidation film thickness of about 10 nm.

[0036] (6) As shown in FIG. 2F, by using a wet etching with dilutedhydrofluoric acid, chemical dry etching (CDE) or hydrogen fluoride vaporphase cleaning (VPC), the HDP film 7 deposited on the side faces isremoved by etching until the side face of the trench 5 has been exposed.At the same time, the full surface of each the HDP films 6 and 7 areetched in an isotropic manner, and the top surface of the HDP film 6 isalso retracted to some extent. However, etching to an extent can ensuresubstantial film thickness such that the HDP film 7 of the side face isremoved. For example, if the 30 nm thick film 7 on the side face part isremoved, the upper part of the film 6 is removed by a depth of about 30nm. However, this elimination is merely 10% of the 300 nm originaldepth, and a depth of 270 nm is left.

[0037] Therefore, after the HDP film 7 deposited on the side faces hasbeen removed, the HDP film 6 is deposited on the bottom of the trench 5at a substantial film thickness. If a HDP film 8 is further deposited inthis state, it is possible to fill in a trench 5 exceeding an aspectratio of 3 in the HDP film without void.

[0038] (7) As shown in FIG. 2G, the HDP film 8 is further deposited. Indepositing the HDP film 8, the trench 5 is filled in with the HDP film6, and the aspect ratio is lowered. Thus, no void is produced in thetrench 5. In the trench with very high aspect ratio, if a void isproduced again during the second deposition of the HDP film 8, the HDPfilm 8 is deposited again before the HDP film 8 on the side faces closesup the opening of the trench 5. The HDP film 8 on the side faces isetched, and again, another HDP film is deposited. Then, by repeatingthis procedure of deposition and etching, it is possible to completelyfill in the trench 5 with the HDP films 6 and 8.

[0039] (8) Then, as shown in FIG. 2H, silicon oxide films 8 and 7 arepolished up to the height of the mask 3 according to a chemicalmechanical polishing (CMP) technique.

[0040] (9) As shown in FIG. 2I, the surface of an oxide film 9 is thenlowered by an etching treatment using diluted hydrofluoric acid (HF).Then, as shown in FIG. 2J, the mask 3 is removed. Lastly, as shown inFIG. 2K, the buffer oxide film 2 is removed. In this way, the STI areas6 and 9 can be formed.

[0041] A hydrofluoric acid etching rate of the HDP films 6 and 9 withoutheat treatment after deposition is equal to that of a thermal oxidefilm. The HDP films 6 and 9 are uniform, fine, and free fromhumidification. In this respect, unlike a silicon oxide film formedaccording to an earlier CVD technique or spin-on glass (SOG) technique,these HDP films 6 and 9 are suitable for the insulating film of the STIarea. In addition, there is an advantage in that the trench with anaspect ratio of about 3 can be filled, and these HDP films have beenoptimal for use as such STI insulating film. According to themanufacturing method of the semiconductor device of the firstembodiment, it is possible to fill in with a HDP film the trench with ahigh aspect ratio exceeding 3 which cannot be filled in the earlier HDPfilm. Then, an STI area with a high aspect ratio exceeding 3 resultingfrom the shrink of semiconductor devices can be manufactured using theHDP film.

[0042]FIG. 2K is a sectional view showing a semiconductor device of thefirst embodiment. The semiconductor device of the first embodiment iscomposed of a semiconductor substrate 1, a bottom insulator 6, and anupper insulator 9. The semiconductor substrate 1 has a trench 5 formedon the surface. The upper insulator 9 has a bottom face that comes intocontact with the upper face of the bottom insulator 6 and a side facethat comes into contact with the side face of the trench 5. The upperinsulator 9 has a bottom face that comes into contact with the upperface of the bottom insulator 6 and a side face that comes into contactwith the side face of the trench 5. The insulators 6 and 9 are laminatedand filled into the trench 5, whereby the insulators 6 and 9 serve as anisolation area.

[0043] (Second Embodiment)

[0044] In the first embodiment, in the shape produced after the HDP film7 on the side face of the trench 5 has been etched, the HDP film 7deposited on the mask 3 is rounded as shown in FIG. 2F. When the secondHDP film 8 is deposited, ions which fly upward from this roundeddiagonal point are reflected. The rounded HDP film 7 enables thedeposition on the side faces of the trench 5. Thus, the limit forfilling the void-free trench 5 with the HDP film 8 on the second fillingis inferior to the limit of filling a void-free simple trench with norounding. In order to further increase the filling limit for when thesecond HDP film 8 is deposited, the following process is added beforedepositing the second HDP film 8.

[0045] Hereinafter, a method for manufacturing a semiconductor deviceaccording to a second embodiment will be described. The semiconductordevice manufacturing method according to the second embodiment isidentical to that according to the first embodiment in the stages (1) to(6) shown in FIG. 2F.

[0046] (1) Next, as shown in FIG. 3A, a photo resist 10 is applied.

[0047] (2) When this resist 10 is exposed and developed to some extent,as shown in FIG. 3B, a resist 11 can be lowered so that only the resist11 in the trench 5 remains. In addition, this lowering can be achievedby fully etching back the resist 10 according to a CDE technique.

[0048] (3) As shown in FIG. 3C, only the HDP film 7 on the mask 3 at theopening face of a so called trench 5 is selectively removed according todiluted hydrofluoric acid wet etching treatment or a CDE technique,until this opening face is exposed.

[0049] (4) As shown in FIG. 3D, the photo resist 11 in the trench 5 isselectively removed according to the CDE technique.

[0050] (5) As shown in FIG. 3E, the HDP film 8 is further deposited. Indeposition of the HDP film 8, there is no rounded HDP film 7 formed onthe mask 3. Thus, after the HDP film 6 has been deposited on the bottomof the trench 5, if the aspect ratio of a trench free of being filled is3 or less, the trench can be completely filled in the second filling ofthe HDP film 8. In a trench with a very high aspect ratio, if a void isproduced again when the second HDP film 8 is deposited, themanufacturing method of the second embodiment is repeated again, therebymaking it possible to completely fill a trench with the HDP film.

[0051] Lastly, as in the first embodiment, as shown in FIG. 2H in thestage (8), a silicon oxide film 8 is polished according to the CMPtechnique down to the height of the mask 3. As shown in FIG. 2I to FIG.2K of the stage (9), the surface of the oxide film 9 is lowered, themask 3 is removed, and the buffer oxide film 2 is removed. Accordingly,the STI areas 6 and 9 can be formed.

[0052] (Third Embodiment)

[0053] In the third embodiment, there is provided a semiconductor devicemanufacturing method capable of preventing damage to the siliconsubstrate 1 when the HDP film 6 is deposited. As a first stage, beforefilling with the HDP film 6, the internal surface of the trench 5 isoxidized by the oxidation film thickness to about 10 nm, and the oxidefilm 12 is formed, as shown in FIG. 4A. As shown in FIG. 4C, in removingthe HDP film 7 deposited on the side face, the oxide film 12 located atthe upper part in such trench 5 is also reduced at the same time. If thesecond HDP film 8 is deposited in this state, a silicon substrate 1 isexposed during the second deposition, thus making it impossible toprevent damage to the silicon substrate 1 when the HDP film 8 isdeposited. Therefore, as a countermeasure against damage at the secondstage, before filling with the second HDP film 8, as shown in FIG. 4D,the oxidation of the exposed silicon substrate 1 is carried out again,and the oxide film 33 with 10 nm thickness is formed. Countermeasuresagainst damage at these two stages are added to the semiconductor devicemanufacturing method, thereby making it possible to prevent damage tothe silicon substrate 1 when the HDP films 6 and 8 are deposited.

[0054] Lastly, as in FIG. 2H of the stage (8) according to the firstembodiment, as shown in FIG. 4F, the silicon oxide films 8 and 7 arepolished according to the CMP technique so that the height of thesurface of the silicon oxide films 8 and 7 is equal to that of the mask3. As in FIG. 2I to FIG. 2K of the stage (9), first, as shown in FIG.4G, the surface of the oxide film 9 is lowered, and the mask 3 isremoved. As shown in FIG. 4H, the buffer oxide film 2 is removed. Indoing this, the STI areas 6 and 9 can be formed.

[0055] The semiconductor device according to the third embodiment, asshown in FIG. 4H, has a semiconductor substrate 1, an insulating film12, a bottom insulator 6, an insulating film 33, and an upper insulator9. The semiconductor substrate 1 has a trench 5 on the surface. Theinsulating film 12 has a bottom face that comes into contact with thebottom face of the trench 5 and with the lower part of the side face ofthe trench 5. The bottom insulator 6, at the bottom face and the sideface, comes into contact with the surface of the insulating film 12. Theinsulating film 33, at the back face, comes into contact with the upperpart of the side face of the trench 5, and the insulation film, at theend face, comes into contact with that of the insulating film 12. Theupper insulator 9, at the side face, comes into contact with the surfaceof the insulating film 33. The upper insulator 9, at the bottom face,contacts with the upper face of the bottom insulator 6.

[0056] The semiconductor device of the third embodiment is useful whenthe trench 5 of the semiconductor substrate 1 exceeds an aspect ratio ofabout 3. The insulating films 12 and 33 is formed on the surface of thetrench 5 formed on the surface of the semiconductor substrate 1, theinsulators 6 and 9 are laminated and filled into the inside of thetrench 5, whereby the STI area 6, 9, 12 and 33 can be formed.

[0057] (Fourth Embodiment)

[0058] In the fourth embodiment, as in the third embodiment, an objectof the present embodiment is to prevent damage to the silicon substrate1 when the HDP film is deposited. In particular, in the case where theinside of the trench 5 is oxidized before filling the HDP film 6, whenthe HDP film 7 deposited on the side faces is removed, the oxide film 12formed in the trench 5 before filling the HDP film 6 is also removed atthe same time. If the second HDP film is deposited in this state, thesilicon substrate 1 is exposed during the second deposition, thus makingit impossible to prevent damage to the silicon substrate 1 when the HDPfilm 8 is deposited.

[0059] Therefore, in the case where the inside of the trench 5 isoxidized, after the oxidation stage shown in FIG. 4A of the thirdembodiment, additionally, as shown in FIG. 5A, a silicon nitride film(Si3N4) is deposited by about 10 nm, or preferably, 6 nm according tothe LPCVD technique. Then, manufacturing is carried out as follows inthe first and second embodiments.

[0060] (1) As shown in FIG. 5B, HDP films 6 and 7 are deposited in thistrench 5. (2) As shown in FIG. 5C, the HDP film 7 deposited on the sidefaces is removed by etching. The HDP film 7 is etched while selectivityis provided by a silicon nitride film 13, due to etching processing suchas with a diluted hydrofluoric acid, whereby the silicon oxide film 12formed on the side face of the trench 5 before filling the HDP film 6remains without being etched.

[0061] (3) Next, as shown in FIG. 5D, a photo resist 10 is applied. (4)As shown in FIG. 5E, a photo resist 11 remains only in the trench 5. (5)As shown in FIG. 5F, only the HDP film 7 that is on the mask 3 isremoved. (6) As shown in FIG. 5G, the photo resist 11 in the trench 5 isremoved. (7) As shown in FIG. 5H, an HDP film 8 is further deposited.(8) As shown in FIG. 5I, a silicon oxide film 8 is polished according tothe CMP technique down to the height of the mask 3.

[0062] (9) As shown in FIG. 5J and FIG. 5K, the surface of the oxidefilm 9 is lowered, the mask 3 is removed, and the buffer oxide film 2 isremoved. Accordingly, the STI areas 6 and 9 can be formed. In addition,a layer damaged by formation of the HDP film is not formed in thesubstrate 1.

[0063] The semiconductor device according to the fourth embodiment, asshown in FIG. 5K, is composed of: a semiconductor substrate 1; a siliconoxide film 12; a silicon nitride film 13; a bottom insulator 6; and anupper insulator 9. The semiconductor substrate 1 has a trench 5 on thesurface. The silicon oxide film 12 has a back face that comes intocontact with the bottom face and side face of the trench 5. The siliconnitride film 13, at the back face, comes into contact with the surfaceof the silicon oxide film 12. The bottom insulator 6, at the bottom faceand side face, comes into contact with the surface of the siliconnitride film 13. The upper insulator 9, at the side face, comes intocontact with the surface of the silicon nitride film 13, and the upperinsulator 9, at the bottom face, comes into contact with the upper faceof the bottom insulator 6.

[0064] The semiconductor device of the fourth embodiment is useful whenthe trench 5 of the semiconductor substrate 1 exceeds the aspect ratioof about 3. The insulating films 12 and 13 laminated on the surface ofthe trench 5 formed on the surface of the semiconductor substrate 1 areformed, the insulators 6 and 9 are filled into and laminated inside ofthe trench, whereby an STI area 6 and 9 can be formed.

[0065] (Fifth Embodiment)

[0066] When STI area is formed in the fourth embodiment, as shown inFIG. 5K, the STI internal surfaces formed with a laminate of a thinsilicon oxide film 12 and a thin silicon nitride film 13 on the inside.In this case, charge can be trapped at the interface state of an oxidefilm 12-nitride film 13 interface. Such charge, in particular, a chargelocated in the vicinity of the surface of the substrate 1 affects theelectric field of an element area. There is a possibility that anunexpected behavior can be produced in the operation of a semiconductordevice.

[0067] As a result, in the fifth embodiment, in order to avoid the abovedescribed concern, the silicon nitride film 13 located in the vicinityof the surface of the substrate 1 is removed.

[0068] That is, after removing the photo resist 11 in the trench 5 shownin FIG. 5G of the fourth embodiment, as shown in FIG. 6A, the exposedsilicon oxide film 13 is removed. As shown in FIG. 6B, the HDP film 8 isadditionally deposited. As shown in FIG. 6C, the silicon oxide film 8 ispolished according to the CMP technique down to the height of the mask3. As shown in FIG. 6D, the surface of the oxide film 9 is lowered, andthe mask 3 is removed. As shown in FIG. 6E, the buffer oxide film 2 isremoved. In doing this, the isolation areas 6 and 9 caused by STI areacan be formed.

[0069] After removing the film 7 on the side face of the trench 5 shownin FIG. 5C of the fourth embodiment, as shown in FIG. 6F, the exposedsilicon nitride film 13 may be removed. In order to remove the film 13,etching may be carried out with hot phosphoric acid. Then, the secondHDP film 8 is deposited, whereby the above described concern can beavoided.

[0070] The semiconductor device according to the fifth embodiment, asshown in FIG. 6E, is composed of: a semiconductor substrate 1; a siliconoxide film 12; a silicon nitride film 13; a bottom insulator 6; and anupper insulator 9. The semiconductor substrate 1 has a trench 5 on thesurface. The silicon oxide film 12 has a back face that comes intocontact with the bottom face and side face of the trench 5. The siliconnitride film 13, at the back face, comes into contact with the surfaceof the silicon oxide film 12. The bottom insulator 6, at the bottom faceand side face, comes into contact with the surface of the siliconnitride film 13. The upper insulator 9, at the side face, comes intocontact with the surface of the silicon oxide film 12, and the upperinsulator 9, at the bottom face, comes into contact with an upper faceof the bottom insulator 6 and an end face of the silicon nitride film13.

[0071] The semiconductor device of the fifth embodiment is useful whenthe trench 5 of the semiconductor substrate 1 exceeds an aspect ratio ofabout 3. The insulating films 12 and 13 laminated on the surface of thetrench 5 formed on the surface of the semiconductor substrate 1 areformed, and the insulators 6 and 9 are filled in and laminated inside ofthe trench, whereby the STI area 6 and 9 can be formed.

[0072] (Sixth Embodiment)

[0073] The sixth embodiment can be applied to a method for manufacturinga non-volatile memory cell. In the sixth embodiment, a gate electrode 15consisting of polysilicon of FIG. 7A is formed in a self alignmentmanner together with the trench 5 which serves as STI area. In doingthis, the aspect ratio of the trench 5 is increased. A method forfilling the trench 5 will be described. The sixth embodiment can beapplied to an electric field effect transistor (FET) or the like withoutbeing limited to a nonvolatile memory cell.

[0074] First, as shown in FIG. 7A, on the silicon substrate 1, there aresequentially laminated: an oxide film 2 of 10 nm thick that serves as atunnel oxide film with the nonvolatile memory cell; polysilicon 15 thatserves as a part of a floating gate; and a silicon nitride film thatserves as a cap 3.

[0075] Next, the trench 5 is dug in an area serving as an isolation areaaccording to a lithography process and etching. Specifically, the cap 3,the floating gate 15, the silicon oxide film 2, and substrate 1 aresequentially etched. The isolation trench 5 and the films 3 and 15 areformed in a self alignment manner. A depth of the isolation trench 5 tobe dug in the substrate 1 is obtained as a depth of 300 nm, for example.

[0076] Next, as shown in FIG. 7B, in order to prevent damage to thesubstrate 1 when the HDP film 8 is deposited, before filling with theHDP film 8, the inside of the trench 5 is oxidized in advance of athickness of about 10 nm. This oxidation is carried out by ozone (O3)oxidation. In a general thermal oxidation technique using oxygen orvapor deposition, polysilicon 15 has a higher oxidation rate than thesilicon substrate 1, and polysilicon 15 is oxidized more than thesubstrate 1. Thus, polysilicon has a greater oxide film thickness, theopening is narrowed, and filling properties are degraded. In ozoneoxidation, the difference in oxidation rate between polysilicon andsilicon is small, and filling properties can be improved withoutreducing the size of the opening. Ozone oxidation of the substrate 1 maybe used to form a film 12 of FIG. 4A and a film 33 of FIG. 4D. Theplanar orientation dependency in oxidation rate is small, and thus, auniformly thin film can be formed.

[0077] As shown in FIG. 7C, an HDP film 8 is deposited. The filmthickness of the oxide film 16 is not large even on the side face ofpolysilicon 15. Thus, an opening is not narrowed, and the fillingproperties are not degraded. In the case where ozone oxidation is used,the filling properties are improved even when the silicon oxide film isfilled according to an LP-tetra ethyl ortho silicate (TEOS) technique,for example. The optimum improvement in filling that can be produced byozone oxidation includes the filling properties of the trench 5 of FIG.4A without polysilicon 15. That is, although filling properties areimproved by ozone oxidation, even in a case where ozone oxidation iscarried out, when the aspect ratio exceeds about 3, it becomes necessaryto use the filling method described in the first to fifth embodiments tofill the HDP film.

[0078] In the sixth embodiment, ozone oxidation was carried out for theoxidation of the inside of the trench 5, there is provided a featurethat since a difference in oxidation rate between polysilicon 15 and asilicon substrate 1 is small, in the first and second oxidationtechniques shown below, an improvement in filling properties similar tothat of ozone oxidation can be seen.

[0079] The first oxidation technique is directed to a method forcombusting hydrogen (H₂) and oxygen (O₂) immediately above the siliconsubstrate 1 or the like, followed by combusting and oxidizing thesubstrate 1.

[0080] The second oxidation technique is directed to a method forproducing an oxygen radial (O*) by using a catalyst, followed byoxidizing the silicon substrate 1 or the like by using this oxygenradial.

[0081] The ozone oxidation and the first and second oxidation techniquesare common to each other in that an oxygen radial is generated, and asilicon substrate 1 or the like is oxidized by this oxygen radical. Inozone oxidation, one oxygen atom of the three oxygen atoms (O)configuring ozone is liberated, and an oxygen radial is generated. Incombustion and oxidation immediately above an oxide, an oxygen radicalwith the short service life can be supplied to the substrate 1 or thelike, and the oxygen radical is obtained as a primary oxidizer. Theoxygen radical has a large oxidation force, and oxidation reactioneasily occurs due to this oxidation force, and the oxidation rate israte-determined to supply the oxygen radical. In this manner, inoxidation due to the oxygen radical, a substantially equal oxidationrate is obtained in a polysilicon 15 and a silicon substrate 1, whichcan be considered as equal to the supply quantity of oxygen radical.

[0082] As shown in FIG. 7D, the silicon oxide film 8 is polishedaccording to the CMP technique down to the height of the mask 3. Asshown in FIG. 7E and FIG. 7F, the surface of the oxide film 9 islowered. As shown in FIG. 7E and FIG. 7F, the mask 3 is removed. Indoing this, the STI areas 16 and 9 can be formed.

[0083] The semiconductor device according to the sixth embodiment, asshown in FIG. 7F, is composed of: a semiconductor substrate 1; aninsulating film 2; a polysilicon film 15; a silicon oxide film 16; andan insulator 9. The semiconductor substrate 1 has a trench 5 on thesurface. The insulating film 2 is provided so that the back face comesinto contact with the surface top of the substrate 1, and has an openingon the trench 5. The polysilicon film 15 is provided on the surface ofthe insulating film 2, and has an opening on the trench 5. The siliconoxide film 16 has a back face that comes into contact with the bottomface and side face of the trench 5 and that comes into contact with theside face of the opening of the film 15, and the film thickness isuniform. The insulator 9, at the bottom face and side face, comes intocontact with the surface of the silicon oxide film 16.

[0084] (Seventh Embodiment)

[0085] In the seventh embodiment, as in the third embodiment, the objectis to prevent damage to the silicon substrate 1 when the HDP film isdeposited. In particular, in a case where the inside of the trench 5 isoxidized before filling the HDP film 7, when the HDP film 7 deposited onthe side face is removed, an oxide film 12 formed in the trench 5 isalso removed at the same time before filling with the HDP film 8. If asecond HDP film 8 is deposited in this state, the silicon substrate 1 isexposed during the second deposition, thus making it possible to preventdamage to the silicon substrate 1 when the HDP film 8 is deposited.

[0086] Therefore, in the case where the inside of the trench 5 isoxidized, after the oxidation process of FIG. 4A in the thirdembodiment, next, as shown in FIG. 8A, the HDP film 7 is filled into thetrench 5 with a high aspect.

[0087] Next, as shown in FIG. 8B, the HDP film 7 formed on the mask 3 isremoved according to the CMP technique until the opening of the trench 5has been exposed. At this time, the HDP film 38 on the side face remainsas it is, and thus, the oxide film 12 is not removed.

[0088] Then, as shown in FIG. 8C, the HDP film 8 is deposited onceagain. The aspect ratio of the trench 5 is lowered by removing the HDPfilm 7 on the mask 3 according to the CMP technique. Thus, the HDP film8 is deposited in this state, thereby making it possible to fill thetrench 5 with a high aspect ratio without producing a void. The trench 5with a high aspect ratio that can not be filled in with the HDP filmconventionally can here be filled in with the HDP films 7 and 8.

[0089] As shown in FIG. 8D, the silicon oxide film 8 is polishedaccording to the CMP technique down to the height of the mask 3. Theinsulators 38 and 39 are filled in the trench 5.

[0090] As shown in FIG. 8E, the surface of the oxide films 38 and 39 areeach lowered by wet processing such as with a diluted hydrofluoric acid.As shown in FIG. 8F, the mask 3 is removed, and the buffer oxide film 2is removed. In doing this, the isolation areas 38 and 39 formed by STIarea can be produced. In addition, there is no possibility of a damagelayer being formed due to the formation of the HDP film 8 in thesubstrate 1.

[0091] The semiconductor device according to the seventh embodiment, asshown in FIG. 8F, has: a semiconductor substrate 1; a silicon oxide film12; a bottom insulator 38; and an upper insulator 39. The semiconductorsubstrate 1 has a trench 5 on the surface. The silicon oxide film 12 hasa back face that comes into contact with the bottom face and side faceof the trench 5. The bottom insulator 38, at the bottom face and sideface, comes into contact with the surface of the silicon oxide film 12.The upper insulator 39, at the bottom face and side face, comes intocontact with the surface of the bottom insulator 38.

[0092] In the case where the trench 5 of the semiconductor substrate 1exceeds an aspect ratio of about 3, the semiconductor device of theseventh embodiment is more effective. The insulating film 12 laminatedon the surface of the trench 5 formed on the surface of the surface ofthe semiconductor substrate 1 is formed, the bottom insulator 38 isfilled into the trench 5, and the upper insulator 39 is filled into thebottom insulator 38, whereby the isolation areas 38 and 39 can beformed.

[0093] The HDP film has a hydrofluoric acid etching rate identical to athermal oxide film even if heat treatment is applied after deposition.In addition, there is an advantage in that a trench with a to someextent high aspect can be filled. This film is optimal for use in STIinsulating film. According to the present invention, it is possible tofill with the HDP film a trench with a high aspect ratio that cannot befilled with an HDP film conventionally. Thus, STI area with a highaspect ratio caused by the continuing miniaturization of thesemiconductor devices can be manufactured with an HDP film.

[0094] (Eighth Embodiment)

[0095] In the eighth embodiment, a method of filling between gateelectrodes of a semiconductor device will be described. The HDP film isfilled between gate electrodes forming a trench with a high aspectratio. First, the HDP film is filled in a trench with the high aspect.Next, the etching of the HDP film deposited in the vicinity of theopening of the trench and depositing the HDP film again are repeatedonce or a plurality of times. In doing this, a trench with a high aspectthat cannot be filled with the HDP film conventionally, here can befilled with the HDP film.

[0096] (1) First, as shown in FIG. 9A, on a p-type silicon (Si)substrate 1, there are sequentially deposited: an oxide film 2 having a10 nm tunnel oxide film of nonvolatile memory cells; a polysilicon 15serving as a floating gate; an oxide nitride oxide (ONO) film 17; apolysilicon film 18 and a tungsten silicide (WSi) film 19 that serve asa control electrode; and a silicon nitride film 3 that serves as a cap.

[0097] (2) Next, a gate electrode is separated for each element. Asshown in FIG. 9B, a trench 5 is formed according to the lithographyprocess and etching. Specifically, the cap material 3, WSi film 19,polysilicon 18, ONO film 17, polysilicon 15, and tunnel oxide film 2 aresequentially etched.

[0098] (3) As shown in FIG. 9C, oxide films 20 to 22 are formedaccording to a thermal oxidation technique, for example. This filmthickness is obtained as film thickness of 10 nm, for example.

[0099] (4) As shown in FIG. 9D, the cap material 3 is defined as a maskwhile the substrate 1 is subjected to ion implantation, thereby formingan n-type semiconductor area 23.

[0100] (5) As shown in FIG. 9E, a silicon nitride film is formed at afilm thickness of about 20 nm according to the CVD technique, and fullyetched back according to a reactive ion etching (RIE) technique, therebyforming a spacer layer 24 of the silicon nitride film.

[0101] (6) As shown in FIG. 9F, the cap material 3 is defined as a maskwhile the substrate 1 is subjected to ion implantation, thereby formingan n-type semiconductor area 25. In doing this, semiconductor areas 23and 25 each serving as a source-drain area can be formed.

[0102] (7) As shown in FIG. 9G, the HDP film 6 is filled in the trench5. The HDP films 6 and 7 are deposited immediately before the HDP film 7filled at the upper part of the side face of the trench 5 closes theopening of the trench 5. For example, if an opening width is 60 nm, ifthe film thickness is deposited by about 200 nm, the depth filled in theHDP film 6 is also obtained at about 200 nm. Then, the film thickness ofthe side face part of the HDP film 7 is about 20 nm which is about{fraction (1/10)} thereof. If a film 7 of 20 nm is deposited on the sidefaces of both sides of the trench 5 with an opening width of 60 nm, theremaining opening is 10 nm.

[0103] (8) As shown in FIG. 9H, the HDP film 7 deposited on the sidefaces is removed by etching, by using wet etching processing such asdiluted hydrofluoric acid, CDE, or alternatively, a hydrogen fluoridevapor phase cleaning (VPC) technique and the like. At the same time, thefull surface of the HDP films 6 and 7 are each etched in an isotropicmanner, and the top face of the film 6 is also retracted to some extent.For example, when the film 7 on the side faces of 20 nm in filmthickness is removed, the upper part of the film 6 is also removed by adepth of about 20 nm. However, this removal is merely 10% of theoriginal depth of 200 nm, and a depth of 180 nm is left as it is.

[0104] (9) Next, a photo resist is fully applied, and a resist 10 isfully etched back according to the CDE technique. As shown in FIG. 9I, aresist 11 remains only in the trench 5.

[0105] (10) As shown in FIG. 9J, only the HDP film 7 on the mask 3 isselectively removed according to wet etching processing such as dilutedhydrofluoric acid.

[0106] (11) As shown in FIG. 9K, the photo resist 11 in the trench 5 isselectively removed according to the CDE technique.

[0107] (12) As shown in FIG. 9L, an HDP film 26 is further deposited.Deposition of the HDP film 26 can be carried out as with the film 6.That is, the opening width is 60 nm the same as during deposition, andthus, a film thickness of about 200 nm can be deposited, and the depththat can be filled in the HDP film 26 is also obtained at about 200 nm.The film thickness of the side face part of the HDP film 27 is alsoobtained as about 20 nm, and thus, an opening is also left of about 10nm. The total filling depth when the films 6 and 26 are added to eachother reaches 380 nm.

[0108] (13) As shown in FIG. 9M, the HDP film 27 deposited on the sideface is removed by etching using wet etching processing such as adiluted hydrofluoric acid. At the same time, the full surface of the HDPfilms 26 and 27 are each etched in an isotropic manner, and the top faceof the film 6 is also retracted to some extent. If the film 27 on theside faces of 20 nm in film thickness is removed, the upper part of thefilm 26 is also removed by a depth of about 20 nm. However, this removalis merely 10% of the original depth of 200 nm, and a depth of 180 nm isleft, and the total of depths when the films 6 and 26 are added togetheris 360 nm.

[0109] (14) Next, the stages (9) to (11) are executed again, and onlythe HDP film 27 on the mask 3 is removed as shown in FIG. 9N.

[0110] (15) As shown in FIG. 9O, the HDP film 8 is further deposited. Indeposition of the HDP film 8, the remaining depth of the trench 5 leftunfilled is 160 nm, the opening width is 60 nm, and the aspect ratio is3 or less. Thus, the trench 5 can be completely filled by the depositionof the HDP film 8.

[0111] (16) Lastly, as shown in FIG. 9F, the silicon oxide film 8 ispolished according to the CMP technique down to the height of the mask3.

[0112] As shown in FIG. 9P, the semiconductor device according to theeighth embodiment is a semiconductor device having the nonvolatilememory cell. The nonvolatile memory cell is composed of: a semiconductorsubstrate 1; a plurality of gate electrodes; insulating films 6, 26, and9. The gate electrode is provided at the upper part of the substrate 1.The insulating films 6, 26, and 9, at their side faces, come intocontact with the side faces of a plurality of gate electrodes, and arecomposed of insulating films 6, 26, and 9 laminated on the substrate 1,respectively.

[0113] Semiconductor areas 23 and 25, of a different electricalconduction type from the substrate 1 serving as a source-drain area,exist at the upper part of the substrate 1. The gate electrode iscomposed of: an oxide film 2 of 10 nm in film thickness serving as atunnel oxide film of the nonvolatile memory cell on the substrate 1;polysilicon film 15 of 125 nm in film thickness serving as a part of thefloating gate on the film 2; an insulating film 17 such as an ONO filmof 10 nm in film thickness on such polysilicon film 15; polysilicon film22 of 125 nm in film thickness serving as a control electrode on thefilm 17; a WSi film 19 of 100 nm in film thickness; a silicon nitridefilm 3 of 150 nm in film thickness that serves as a cap on the film 19;and a silicon nitride film 24 of 20 nm in film thickness that serves asa spacer provided on a side face thereof. The pitch of the gateelectrode is 200 nm, and the line and spaces are 100 nm and 100 nm. In atrench having the semiconductor substrate 1 defined as a bottom face andhaving the side faces of a plurality of gate electrodes defined as aside face, the opening width is 60 nm, the depth is 520 nm, and theaspect ratio exceeds 3 and reaches 8. The eighth embodiment can beapplied to an electric field effect transistor (FET) or the like withoutbeing limited to a nonvolatile memory cell.

[0114] (Ninth Embodiment)

[0115] In the ninth embodiment, a method for filling between metalinterconnections of a semiconductor device will be described here. In amethod for manufacturing a semiconductor device according to the ninthembodiment, an HDP film is filled between metal interconnections forminga trench with the high aspect ratio.

[0116] (1) First, as shown in FIG. 10A, an inter-layer insulating film28, a titanium nitride (TiN) film 29, an aluminum (Al) alloy film 30,and a titanium nitride film 31 are sequentially deposited on a siliconsubstrate 1.

[0117] (2) Next, as shown in FIG. 10B, a trench 5 is dug according to alithography process and etching. Specifically, the titanium nitride film31, aluminum alloy film 30, and titanium nitride film 29 aresequentially etched. Then, the etched films separate eachinterconnection.

[0118] (3) As shown in FIG. 10C, an HDP film 6 is filled in this trench5. The temperature of the substrate 1 during filling is set to about450° C. The temperature is reduced to be lower than 650° C. according tothe first and second embodiments, although the filling properties aredegraded. This is because the upper limit of the heat resistancetemperature of an aluminum alloy film 30 is about 450° C. The degree ofdegradation of filling properties is lowered from about 3 of 650° C. toabout 2 of 650° C. for aspect ratios at which filling is possible. TheHDP films 6 and 7 are deposited immediately before the HDP film 7deposited at the upper part of the side face of the trench 5 closes theopening of the trench 5. With an opening width is 100 nm, if the film isdeposited at a film thickness of about 150 nm, the depth filled in theHDP film 6 is also defined as about 150 nm, and the film thickness ofthe side face part of the HDP film 7 is about 30 nm which is about ⅕thereof. When the film 7 of 30 nm is deposited on the side face on bothsides of a trench 5 of 100 nm in opening width, the remaining opening is40 nm

[0119] (4) As shown in FIG. 10D, the HDP film 7 deposited on the sidefaces is removed by etching using the CDE technique. At the same time,the full surfaces of the HDP films 6 and 7 are each etched in anisotropic manner, and the upper face of the film 6 is also retracted tosome extent. For example, if the film 7 at the side faces part of 30 nmin film thickness is removed, the upper part of the film 6 is alsoremoved by a depth of about 30 nm. However, this removal is merely 20%of the original depth of 150 nm, and a depth of 120 nm remains.

[0120] (5) Next, a photo resist is fully applied, the resist is fullyetched back according to the CDE technique, and the resist 11 is filledin the trench 5, as shown in FIG. 10E.

[0121] (6) As shown in FIG. 10F, with the resist 11 is defined as amask, the CDE technique is carried out, and only the HDP film 7 on theinterconnection 31 is removed.

[0122] (7) As shown in FIG. 10C, the photo resist 11 in the trench 5 isselectively removed according to the CDE technique.

[0123] (8) The HDP film 8 is further deposited as shown in FIG. 10H. Indeposition of the HDP film 8, the remaining depth of the trench 5 freeof being filled is 180 nm, the opening width is 100 nm, and the aspectratio is 2 or less. Thus, the trench 5 can be completely filled in bydeposition of the HDP film 8.

[0124] (9) Lastly, as shown in FIG. 10I, the silicon oxide film 8 isflattened according to the CMP technique.

[0125] As shown in FIG. 10I, the semiconductor device according to theninth embodiment is composed of: an inter-layer insulating film 28; aplurality of metal interconnections 29 to 31; an insulating film 6; andan insulating film 8. The inter-layered insulating film 28 is providedon the semiconductor substrate 1. A plurality of metal interconnections29 to 31 are provided on the film 28. An insulating film 6, at the wideface, comes into contact with the lower side faces of a plurality ofmetal interconnections 29 to 31, and is laminated on the film 28. Theinsulating film 8 comes into contact with an upper side face of aplurality of metal interconnections 29 to 31, and is provided on thefilm 6 and metal interconnections 29 to 31.

[0126] The metal interconnections 29 to 31 are composed of: a titaniumnitride film 29 of 40 nm in film thickness on the film 28; an aluminumalloy film 30 of 240 nm in film thickness on the film 29; and a titaniumnitride film 31 of 20 nm in film thickness on the film 30. The pitchbetween the metal interconnections 29 to 30 is 20 nm, and the line andspace is 100 nm and 100 nm. A trench having the film 28 defined as abottom face and having side faces of a plurality of interconnections 29to 31 defined as a side face is 100 nm in opening width, 300 nm indepth, and 3 in aspect ratio.

[0127] (Tenth Embodiment)

[0128] The tenth embodiment describes a semiconductor devicemanufacturing method capable of manufacturing an isolation area for ahigh voltage resistance circuit in a peripheral circuit area, in theprocess of manufacturing a STI area of a low voltage resistance circuitin an internal circuit area.

[0129] A case of forming a gate electrode and an isolation area in aself alignment manner will be described here. Before forming STI area,ion implantation for forming a well is carried out. At this time, aportion free of ion implantation is masked with a photo resist in orderto limit the ion implantation area. Thus, before ion implantation forforming a well, it is necessary to form a mark for carrying outphotolithography alignment. When such a mark is formed, deep STI areacan be formed at the portion of an isolation area requiring STI areahaving the high isolation resistance.

[0130] The gate element and isolation area for the low voltageresistance circuit and high voltage resistance circuit are formed in aself alignment manner. At this time, a method for forming STI area withthe high isolation resistance of the high voltage resistance circuitincludes: forming a deep, narrow trench at a portion of the isolationarea requiring deep STI area and filling with an insulating film. Next,the mask and gate insulating film in this isolation area are removed,and the insulating film filled in a deep, narrow trench is etched back.Then, a shallow, wide trench is formed in this isolation area, and aninsulating film is filled in. In this manner, deep SIT can be formed ata portion requiring isolation resistance.

[0131] First, as shown in FIG. 11A, on the semiconductor substrate 1, asilicon oxide film is formed as a buffer insulating film 2 according toa thermal oxidation technique. Next, as a mask 3, for example, a siliconnitride film is deposited according to a thermal CVD technique.

[0132] Then, as shown in FIG. 11B, in the high voltage resistancecircuit area, an opening 41 of a photo resist 4 is formed in a patternshape of an area for forming deep STI area according to aphotolithography technique. In addition, in a mask alignment mark area,an opening 42 having the mark pattern shape is also formed with thephoto resist 4 at the same time. In an internal low voltage resistancecircuit area, the photo resist 4 is fully formed on the mask 3, and anopening is not formed in the resist 4.

[0133] Next, as shown in FIG. 1C, with the photo resist 4 is defined asa mask, a buffer insulating film 2 is etched in a RIE technique. Theopening 42, having the pattern shape of an alignment mark, and theopening 41, having the pattern shape of an area for forming STI area,are formed on the mask 3. On the other hand, in the low voltageresistance circuit area, the mask 3 is not etched during this etching.

[0134] Further, as shown in FIG. 11D, the semiconductor substrate 1 andinsulating film 2 are etched, and a trench 41 of a deep STI area isformed. At the same time, mark sections silicon substrate 1 andinsulating film 2 are etched, and a trench 42 being a mark is formed.The depth from the surface to the bottom of the substrate 1 of thetrench 41 and trench 42 is 0.6 microns. In addition, the width betweenthe trench 41 and trench 42 is 2 microns. On the other hand, the lowvoltage resistance circuit area is masked by the mask 3 during thisetching, and the silicon substrate 1 and insulating film 2 are notetched.

[0135] Then, as shown in FIG. 1E, the isolation insulating films 43 and44 (for example, an HDP film) are filled in this trench 41 and trench44. Further, the insulating films 43 and 44 are polished down to theheight of the mask 3 according to the CMP technique. Then, the surfaceof the oxide films 43 and 44 are each lowered from the surface of themask 3 according to an etching process using diluted hydrofluoric acid(HF). On the other hand, the low voltage resistance circuit area isprotected by the mask 3 during the filling and polishing of these, andthe silicon substrate 1 and insulating film 2 are not polished oretched.

[0136] Then, as shown in FIG. 11F, the mask 3 and buffer oxide film 2are removed.

[0137] Then, ion implantation for forming a well is carried out. First,in a photolithography technique, a pattern of a photo resist 45 limitingan area for ion implantation is formed, as shown in FIG. 11G. Thepattern of the photo resist 45 is disposed so as to align a mark 42formed on the semiconductor substrate 1 and a mark formed on the resist45. Next, ion implantation of impurities is carried out. An ion beam 46is emitted.

[0138] Then, as shown in FIG. 11H, a gate insulating film 47 is formedon the semiconductor substrate 1 according to thermal oxidation. Then,on the insulating film 47, a polysilicon film is deposited as a gateelectrode material 48. Then, on the polysilicon film 48, for example, anitride silicon film is deposited as mask 49.

[0139] As shown in FIG. 11I, openings 51 and 52 in the pattern shape ofSTI area of a photo resist 50 is formed according to thephotolithography technique. The patterns of the openings 51 and 52 ofthe photo resist are disposed so as to align an oxide film 44 being amark with a mark 53 formed on the resist 50.

[0140] Next, as shown in FIG. 11J, with the photo resist 50 is definedas a mask, the mask 49 and gate electrode material 48 are etchedaccording to the RIE technique. The openings 51 and 52 having thepattern shape of an area for forming STI area are formed on the mask 49and gate electrode material 48.

[0141] As shown in FIG. 1K, a gate insulating film 47 to be exposed isetched. Further, insulating films 43 and 44 filled in deep trenches 41and 53 are etched back to some extent.

[0142] Then, as shown in FIG. 11L, the semiconductor substrate 1 isetched, and trenches 51 and 52 being isolation areas are formed. At thistime, in a mark area, the silicon substrate 1 is hardly etched. Thedepth from the surface to bottom of the substrate 1 of the trenches 51and 52 is 0.3 micron. In addition, the width of the trench 52 is between4 microns and 8 microns. As this width increases, large voltageresistance between elements can be produced. Even at a width of about 4microns, a voltage resistance of 20V or more is produced.

[0143] Then, as shown in FIG. 11M, these trenches 51 and 52 and theisolation insulating films 54, 55, and 56 (for example, an HDP film) arefilled in an opening 53 serving as a mark. In this way, deep STI area 43and 55 is formed in the high voltage resistance circuit area requiringhigh isolation resistance. In addition, there is formed an isolationarea using shallow STI area 54 which is advantageous in filling an STIinsulating film. In a mark area, the opening 53 as well is filled withan insulating film 56.

[0144] In the case where a gate electrode and an isolation area are thusformed in a self alignment manner, ion implantation for forming a wellis required before forming STI area. Thus, in the case where the gateelectrode and isolation area are formed in a self alignment manner, itis necessary to form a mark for carrying out photography alignmentbefore ion implantation for forming a well. At the same time when such amark is formed, a deep trench can be formed at a portion requiring STIarea that has the high isolation resistance. Thus, deep STI area andshallow STI area can be produced separately with a slight increase instages.

[0145] As shown in FIG. 1M, a semiconductor device according to a tenthembodiment has a specific structure for each area.

[0146] First, the semiconductor device according to the tenth embodimenthas a semiconductor substrate 1, a silicon oxide film 47, a polysiliconfilm 48, a silicon nitride film 49, and an upper insulator 54 on theinternal low voltage resistance circuit area. The silicon oxide film 47is provided on the semiconductor substrate 1, and is obtained as a gateinsulating film 47. The polysilicon film 48 is provided on the siliconoxide film 47, and serves as a gate electrode 48. A silicon nitride film49 is provided on the polysilicon film 48, and serves as a mask 49. Aninsulating material 54 penetrates the silicon nitride film 49, thepolysilicon film 48, and the silicon oxide film 47, reaches the insideof the substrate 1, and is disposed so as to surround the surface of thesubstrate 1. This upper insulator 54 comes into contact with thesubstrate 1 on the bottom face, and comes into contact with thesubstrate 1 and films 47, 48, and 49 when the side face is defined as aplane. The upper face of the upper insulator 54 is provided on the sameplane as the upper face of the film 49.

[0147] Next, the semiconductor device according to the tenth embodimenthas a semiconductor substrate 1, a silicon oxide film 47, a polysiliconfilm 48, a silicon nitride film 49, an upper insulator 55, and a bottominsulator 43 on the peripheral high voltage resistance circuit area. Thesilicon oxide film 47 is provided on the semiconductor substrate 1, andserves as a gate insulating film 47. The polysilicon film 48 is providedon the silicon oxide film 47, and serves as a gate electrode 48. Thesilicon nitride film 49 is provided n the polysilicon film 48, andserves as a mask 49. The upper insulator 55 penetrates the siliconnitride film 49, the polysilicon film 48, and the silicon oxide film 47,reaches the inside of the substrate 1, and is disposed so as to surroundthe surface of this substrate 1. The bottom insulator 43 is filled inthe substrate in contact with the lower part of this upper insulator 55.The upper insulator 55, on the bottom face, comes into contact with thesubstrate 1 and the bottom insulator 43, and the upper insulator 55, onthe side face comes into contact with the substrate 1 and the bottominsulator 43 on the plane. The upper face of the upper insulator 55 isprovided on the same plane as that of the film 49. The width of theupper insulator 55 is wider than that of the upper insulator 54. A depthfrom the surface of the substrate 1 on the bottom face of the bottominsulator 43 is deeper than the bottom face of the upper insulator 54.The bottom insulator 43, on the bottom face and side face, comes intocontact with the substrate 1, and the bottom insulator 43, on the upperface, comes into contact with the insulator 55.

[0148] Lastly, the semiconductor device according to the tenthembodiment has a semiconductor substrate 1, a silicon oxide film 47, apolysilicon film 48, a silicon nitride film 49, an upper insulator 56,and an insulating film 44 on the mask alignment mark area. The siliconoxide film 47 is provided on the semiconductor substrate 1, and servesas a gate insulating film 47. The polysilicon film 48 is provided on thesilicon oxide film 47, and serves as a gate electrode 48. The siliconnitride film 49 is provided on the polysilicon film 48, and serves as amask 49. The upper insulator 56 penetrates the silicon nitride film 49,the polysilicon film 48, and the silicon oxide film 47, reaches theinside of the substrate 1, and is disposed so as to surround the surfaceof the substrate 1. The insulating film 44 is filled in the substrate 1in contact with the lower part of this upper insulator 56. The upperinsulator 56, on the bottom face, comes into contact with the insulatingfilm 44, and the upper insulator 56, on the side face, comes intocontact with the substrate 1 and the films 47, 48, and 49. The upperface of the upper insulator 56 is provided on the same plane as that ofthe film 49.

[0149] (Eleventh Embodiment)

[0150] The eleventh embodiment can be applied in a method formanufacturing a nonvolatile memory cell. In addition, the eleventhembodiment can be applied in an electric field effect transistor (FET)or the like.

[0151] First, as shown in FIG. 12A, on the silicon substrate 1, thereare sequentially deposited: an oxide film 2 of 10 nm in film thicknessserving as a tunnel oxide film of a nonvolatile memory cell; apolysilicon 15 serving as a part of a floating gate; and a siliconnitride film that functions as a cap material 3.

[0152] Next, as shown in FIG. 12B, the trench 5 is formed in an areaserving as an isolation area according to a lithography process andetching. Specifically, the cap material 3, gate material 15, siliconoxide film 2, and substrate 1 are sequentially etched. The isolationtrench 5 and the films 3 and 15 are formed in a self alignment manner.In this manner, an aspect ratio of the trench 5 increases. A depth ofthe isolation trench 5 dug in the substrate 1 is obtained as a depth of300 nm, for example.

[0153] As shown in FIG. 12C, in order to prevent damage to the substrate1 during deposition of an HDP film 7, the inside of this trench 5 isoxidized in advance to a film thickness of about 10 nm before fillingthe HDP film 7. This oxidation is carried out according to an oxygen orsteam thermal oxidation technique. This oxidation may be carried out byozone (O3) oxidation. In accordance with this oxidation, silicon oxidefilms 12 and 60 are formed on the internal surface in the trench 5 ofthe exposed silicon substrate 1 and on the side face of the gate 15.

[0154] As shown in FIG. 12D, HDP films 6 and 7 are deposited. On theinternal face of the trench 5 formed on the surface or upward of thesemiconductor substrate 1, the deposition of the silicon oxide films 6and 7 using the HDP technique is begun. Then, before the silicon oxidefilms 6 and 7 closes the opening of the trench 5, the deposition of thesilicon oxide films 6 and 7 is stopped. The height of the lowest site onthe upper face of the silicon oxide film 6 is higher than that of theupper face of the silicon oxide film 2.

[0155] As shown in FIG. 12E, the HDP film 7 deposited on the side faceof the trench 5 is removed by etching. The upper part of the oxide film60 located at the upper part in the trench 5 is also removed at the sametime. After etching, the height at the lowest site of the upper face ofthe silicon oxide film 6 is still higher than that of the upper face ofthe silicon oxide film 2. In this manner, the silicon oxide film 2 isnot etched.

[0156] As shown in FIG. 12F, the second deposition of the HDP film 8 iscarried out. The aspect ratio of the trench 5 is small, thus making itpossible to fill the trench 5 without any void.

[0157] As shown in FIG. 12G, the silicon oxide films 8 and 7 arepolished according to the CMP technique down to the height of the upperface of the mask 3. The mask 3 serves as a stopper according to the CMPtechnique.

[0158] As shown in FIG. 12H, the surface of the HDP film 8 is lowered bywet etching of a diluted hydrofluoric acid. the mask 3 is removed. Inthe foregoing, the STI areas 6 and 12 can be formed.

[0159] In addition, the semiconductor device according to the eleventhembodiment, as shown in FIG. 12H, is composed of: a semiconductorsubstrate 1, a silicon oxide film 2, a polysilicon film 15, a siliconoxide film 12, a bottom insulator 6, a silicon oxide film 60, and anupper insulator 8. The semiconductor substrate 1 has the trench 5 on thesurface. The insulating film 2 is provided so that the back face comesinto contact with the surface top of the substrate 1, and has an openingon the trench 5. The polysilicon film 15 is provided on the surface ofthe insulating film 2, and has an opening on the trench 5. The siliconoxide film 12 comes into contact with the bottom face and side face ofthe trench 5, comes into contact with the side face of the opening ofthe film 2, and is uniform in film thickness. The bottom insulator 6, atthe bottom face and side face, comes into contact with the surface ofthe silicon oxide film 12.

[0160] The silicon oxide film 60, at the back face, comes into contactwith the polysilicon film 15, and the oxide film 60, at the surface,comes into contact with the bottom insulator 6. At one end, the siliconoxide film 60 comes into contact with the silicon oxide film 2. Theheight of the end face at the other end of the silicon oxide film 60 isequal to that of the upper face of the bottom insulator 6. The bottomface of the upper insulator 8 comes into with the other end of thesilicon oxide film 60 and the upper face of the bottom insulator 6. Theside face of the upper insulator 8 comes into that of the polysiliconfilm 15. The silicon oxide film 61 is provided on the polysilicon film15 and the upper insulator 8. It is preferable that the trench 5 of thesemiconductor substrate 1 is equal to or smaller than 3 in aspect ratio.In this manner, when the HDP film 7 deposited on the side face of thetrench 5 is removed by etching, the silicon oxide film 2 serving as thegate oxide layer is not etched.

[0161] As has been described above, there can be provided asemiconductor device having a trench which has a high aspect ratio, thesemiconductor device being filled according to a HDP technique.

[0162] In addition, there can be provided a method for manufacturing asemiconductor device capable of filling according to the HDP technique atrench having a high aspect ratio, the trench being formed in a processof manufacturing a semiconductor device.

[0163] The HDP film is advantageous in that the film has thehydrofluoric acid etching rate identical to the thermal oxide film evenwithout applying heat treatment after deposition, and in that the filmcan fill a trench with a to some extent high aspect. It is possible tofill with the HDP film a trench with a high aspect ratio which cannot befilled with an earlier HDP film. Thus, STI area having the high aspectratio caused by further miniaturization of a semiconductor device can bemanufactured with the HDP film.

[0164] The present invention may be embodied in other specific formswithout departing from the spirit or essential characteristics thereof.The embodiments are therefore to be considered in all respects asillustrative and not restrictive, the scope of the present inventionbeing indicated by the appended claims rather than by the foregoingdescription, and all changes which come within the meaning and range ofequivalency of the claims are therefore intended to be embraced therein.

What is claimed is:
 1. A manufacturing method of a semiconductor device,comprising: forming a trench on a surface of a semiconductor substrate;oxidizing thermally an internal surface of the trench; forming a firstsilicon oxide film into the trench with a high density plasma; removingthe first silicon oxide film formed on a side face of the internalsurface until a part of the side face is exposed; oxidizing thermallythe part of the side face exposed; and forming a second silicon oxidefilm on the first silicon oxide film and on the side face with a highdensity plasma.
 2. The manufacturing method of the semiconductor deviceof claim 1, wherein said removing includes isotropic wet etching.
 3. Amanufacturing method of a semiconductor device, comprising: forming atrench on a surface of a semiconductor substrate; forming a firstsilicon oxide film into the trench with a high density plasma; removingthe first silicon oxide film formed on the surface until the surface isexposed; and forming a second silicon oxide film on the first siliconoxide film and on the exposed surface with a high density plasma.
 4. Themanufacturing method of the semiconductor device of claim 3, whereinsaid removing includes chemical mechanical polishing.
 5. A manufacturingmethod of a semiconductor device, comprising: forming an insulating filmon a semiconductor substrate, forming a polysilicon film on theinsulating film; forming a trench penetrating the insulating film andthe polysilicon film and dug in the semiconductor substrate; forming athermal oxide film on an internal surface of the trench by a oxidationof an oxygen radical; and filling a first silicon oxide film into thetrench with a high density plasma.
 6. The manufacturing method of thesemiconductor device of claim 5, further comprising: removing the firstsilicon oxide film formed on a side face of the internal surface until apart of the side face is exposed; and forming a second silicon oxidefilm on the first silicon oxide film and on the side face with a highdensity plasma.
 7. A manufacturing method of a semiconductor device,comprising: forming an insulating film on a semiconductor substrate;forming a polysilicon film on the insulating film; forming a trenchpenetrating the insulating film and the polysilicon film and dug in thesemiconductor substrate; forming a first thermal oxide film and a secondthermal oxide film by a thermal oxidation of the semiconductor substrateand the polysilicon film on an internal surface of the trench, forming afirst silicon oxide film on the first thermal oxide film and the secondthermal oxide film with a high density plasma; removing the firstsilicon oxide film formed on an upper part of the second thermal oxidefilm; and forming a second silicon oxide film on the first silicon oxidefilm with a high density plasma.
 8. The manufacturing method of thesemiconductor device of claim 7, wherein in said forming the firstsilicon oxide film, a height of a lowest surface of the first siliconoxide film in the trench is higher than a height of a surface of theinsulating film.
 9. A semiconductor device comprising: a semiconductorsubstrate having a trench on a surface; a first insulating filmidentified by a back face contacting with a bottom face and a lower partof a side face of the trench; a bottom insulator identified by a bottomface and a side face contacting with a surface of said first insulatingfilm; a second insulating film identified by a back face contacting withan upper part of the side face of the trench and identified by an endface contacting with an end face of said first insulating film; and aupper insulator identified by a side face contracting with a surface ofsaid second insulating film and identified by a bottom face contactingan upper face of said bottom insulator.
 10. A semiconductor devicecomprising: a semiconductor substrate having a trench on a surface; aninsulating film identified by a back face contacting with the surface ofsaid semiconductor substrate and having a first opening on the trench; apolysilicon film disposed on a surface of said insulating film andhaving a second opening over the trench; a silicon oxide film identifiedby a back face contacting with a bottom face and a side face of thetrench and a side face of the second opening of said polysilicon filmand identified by an uniform film thickness; and an insulator identifiedby a bottom face and a side face contacting with a surface of saidsilicon oxide film.
 11. The semiconductor device of claim 10, wherein anaspect ratio of the trench exceeds three.
 12. A semiconductor devicecomprising: a semiconductor substrate having a first trench on asurface; a silicon oxide film identified by a back face contacting witha bottom face and a side face of the first trench; a bottom insulatoridentified by a bottom face and a side face contacting with a surface ofsaid silicon oxide film and identified by an upper face having a secondtrench; and an upper insulator identified by a bottom face and a sideface contacting with the second trench and identified by a height of anupper face being equal to that of an upper face of said bottominsulator.
 13. A semiconductor device comprising: a semiconductorsubstrate having a trench on a surface; an insulating film identified bya back face contacting with the surface of said semiconductor substrateand having a first opening on the trench; a polysilicon film disposed ona surface of said insulating film and having a second opening over thetrench; a first silicon oxide film contacting with a bottom face and aside face of the trench and a side face of the first opening; a bottominsulator having a bottom face and a side face coming into contact witha surface of the silicon oxide film; a second silicon oxide filmidentified by a back face contacting with said polysilicon film andidentified by a surface contacting with said bottom insulator andidentified by one end contacting with said insulating film andidentified by a height of the other end being equal to that of an upperface of said bottom insulator; and an upper insulator identified by abottom face contacting with the other end of said second silicon oxidefilm and the upper face of said bottom insulator and identified by aside face contacting with a side face of said polysilicon film.